1. Field of the Disclosure
The present disclosure generally relates to the field of semiconductor devices and manufacturing techniques, and more particularly, to semiconductor devices including transistor elements formed on the basis of reduced critical dimensions, such as a gate length, of approximately 50 nm and less.
2. Description of the Related Art
Significant progress has been made in the field of semiconductor devices over the last decades, resulting in semiconductor devices including circuit elements, such as transistors, capacitors, resistors and the like, with critical dimensions in the device level of approximately 50 nm and even less, thereby providing the potential for forming integrated circuits with extremely high integration density. For example, control circuitry including several million transistor elements and more in a single integrated circuit may be fabricated. In other cases, an entire system may be formed on a single chip, thereby requiring the implementation of digital and analog circuit portions, frequently in combination with RF components.
Performance of individual circuit elements and superior integration density have mainly been improved by steadily reducing the lateral dimensions of circuit elements, such as transistor elements, capacitors, resistors, metal features in the metallization system and the like. One very important technology used in the field of semiconductor production is the CMOS technology, according to which transistor elements may be provided in the form of field effect transistors of P-type conductivity and N-type conductivity. Basically, a field effect transistor comprises a channel region, the conductivity of which is controlled by at least one control electrode, typically referred to as a gate electrode, which is connected to an appropriate control voltage. The channel region is, in sophisticated applications requiring extremely efficient small signal transistor elements, formed by a crystalline semiconductor material, typically a silicon or silicon/germanium material, which is connected to current injecting and receiving regions, typically referred to as source and drain regions. The dopant profile in the channel region and the drain and source regions is appropriately adjusted in order to provide a specified amount and direction of current flow between the source and the drain regions upon applying an appropriate control voltage to the gate electrode.
Although basically the continuous reduction of the size of the transistor elements has resulted in extremely high integration density in modern integrated circuits, the introduction of ever decreasing critical dimensions is not a straightforward development. Rather, it appears that many side effects associated with the shrinkage of device dimensions may have to be taken into consideration in order to not unduly offset the general advantages gained by reduced lateral device dimensions and increased packing density.
For example, the transistor elements and any other circuit elements that may be provided in the device level, i.e., in and above a respective crystalline semiconductor layer, such as a silicon layer, have to be appropriately interconnected with respect to the required function of the circuit design under consideration. Consequently, a complex “fabric” of electrical connections has to be provided above the semiconductor-based circuit elements so as to establish the many electrical connections between circuit elements and to the periphery of the integrated circuit or a circuit portion, which may typically be accomplished on the basis of a plurality of metallization layers that have to be provided in a stacked configuration, since typically the number of required interconnections between circuit elements increases over-proportionally with respect to the number of circuit elements.
One important part of the complex structure of connections between circuit elements is represented by so-called contact elements, which may be considered as interface between the plurality of stacked metallization layers and the circuit elements formed in and above the respective semiconductor layer. For example, typically, the drain and/or source regions and the gate electrode structures have to be connected to other circuit elements and/or to the overlying metallization system, which is typically accomplished on the basis of “vertical” highly conductive metal-containing “plugs” formed in a dielectric material system that is formed above and laterally adjacent to the circuit elements of the device level. For sophisticated transistor architectures, which may include transistor elements formed on the basis of critical dimensions of 50 nm, 30 nm and even less, the contacting of transistor elements, and in particular of the drain and source regions, has been identified as a source of significant device failures and thus yield loss.
In view of the situation described above and with respect to the general tendency of further reducing lateral dimensions of sophisticated semiconductor devices, the present disclosure relates to techniques and semiconductor devices in which superior process techniques and/or device characteristics may be provided, while avoiding or at least reducing the effects of one or more of the problems identified above.